High-mobility devices (e.g., Ge-channel, III-V compound-channel devices) are one of the device scaling options considered for 11 nm node and beyond. For System-on-Chip (SoC) applications, in order to meet all the different performance requirements (high performance core CMOS, periphery (analog, I/O), High-voltage devices, ESD, RF) at the same time it is believed that high-mobility devices will have to be co-integrated with standard Si Complementary Metal-Oxide-Semiconductor (CMOS) on silicon substrates.
One solution for pMOS is to form quantum well devices by growing a SiGe or Ge quantum well directly on Silicon. However, III-V compound devices, which have the highest potential for nMOS, need channel material such as, for example, InAs or InGaAs to deliver sufficiently high mobility. These later materials have very large lattice mismatch to silicon, hence requiring growth on a buffer or a stack of layers.
To avoid a loss of foot-print for III-V nMOS devices, the buffer has to be thin enough such that it can fit within a typical shallow trench isolation (STI) trench depth of about 250 to 300 nm. Also all the lattice mismatch defects have to be confined so that they do not propagate to the critical surface region.